Electrically Erasable and Programmable NAND memory has become one of the most popular non-volatile memory (NVM) with the lowest unit price and highest density. Particularly, NAND is extensively used with a big volume in cellular phones, digital cameras, personal digital assistants, mobile computing devices, tablet, SSD, and desktop computers, and many other emerging wearable devices. In order to keep driving NAND density higher at a lower unit cost, the program schemes of MLC, TLC, and even XLC are extensively used in 2D NAND flash memories. Similarly, the 3D NAND flash memory is also migrating from MLC storage in 2013 to TLC storage in 2014 to further reduce the die cost as disclosed by Samsung's Vertical NAND.
Unfortunately, when NAND manufacture technology scaling comes to below 30 nm, or even down to 1×nm-class range, interference coupling effect on the floating-gate charge threshold voltage Vt becomes very severe between two physically adjacent bit lines (BLs) and word lines (WLs) in aforementioned NAND arrays. Thus the NAND data reliability, performance, and P/E endurance cycles of MLC and TLC are greatly degraded compared to SLC storage.
These BL-BL or WL-WL coupling effects are termed as Yupin BL-BL or WL-WL cell coupling effects. The Yupin coupling effect results in erroneous reading, which is not avoidable and much severe particularly in MLC and TLC NAND. In some high-end industry or enterprise SSD code and data storage applications, the high bit errors and low P/E cycles cannot be accepted. Therefore, for a higher reliable NAND code application, a SLC read and storage scheme is still more preferable over the counterparts of MLC, TLC, and XLC storages in storage market place. For example, in 2014, the SLC NAND suppliers include Toshiba's BENAND, Micron, and many other NAND companies such as Spansion, Macronix, Winbond, etc.
In all these conventional SLC NAND designs, an iterative SLC program scheme is generally adopted, which performs a SLC program verification right after each iterative program step to confirm if the SLC program from a single SLC erase state is successfully done. Although this program verification step is advantageous to achieve the narrow width of threshold Vt state distribution and to avoid the over-program of the SLC program, it has several key drawbacks as summarized below. Firstly, the latency of whole cycle of the SLC program operation is about 30% increased when the SLC program verification is required. Secondly, since the high-voltage stress of Vpgm and Vpass of the SLC program cycle and the HV stress of Vread of SLC verification cycle are proportional to the number of iteration steps, thus SLC P/E endurance cycles is drastically reduced. Thirdly, the power consumption of the SLC iterative program and verification are increased proportional to the number of iteration steps, thus battery life is shortened in mobile system equipped with these SLC memory.
For example, the as-mentioned SLC program scheme is based on one typical 2D mainstream NAND array architecture (having a NAND memory block circuit with 1-level tight 1λ-width and 1λ-spacing metal lines (m1) as bit lines (BLs) laid in parallel in Y-direction (string direction) and one common source line (SL) per block laid in X-direction (WL direction). In addition, all BLs including both even-numbered BLe and odd-numbered BLo metal lines are made of same m1 metal layer, but SL uses bottom m0 or m2-strapped layer, depending on the NAND process technologies. With such NAND array structure, all SLC 8 KB NAND cells in all strings in each selected physical WL can be programmed and read at same time in All-BL-manner but at expense of using large size of 8 KB page buffer (PB) and 8 KB static cache registers. Alternatively, Half-BL Odd/Even-numbered BLs read and program can be performed with only one half of interleaving SLC cells associated with half numbers of all BLs on each physical WL are selectively programmed and read at same time with a benefit of using a smaller 4 KB PB but all the latency, gate disturbance, and power consumption of read and program operations are doubled, where Half-BL is referred to interleaving Odd/Even BL-shielding read and program verify operations.
In another example, an alternative NAND array structure includes paired 2D NAND strings as disclosed in U.S. Pat. No. 5,734,609 providing each BL node of Even/Odd string connected in a zigzag way to each corresponding SL node of next adjacent Odd/Even string. But the string size of this NAND array is larger because one depletion-type NMOS transistor with bigger channel length and size is added per string for selecting Even/Odd strings.
Several other conventional NAND structures are proposed (e.g., in U.S. Pat. Nos. 8,695,943 and 7,499,329), but none of those provides truly BL-shielding effect to overcome the Yupin coupling effect at the same time keeping a compact string size in NAND array with small page buffer size.
For many emerging fast program and read applications, a faster and more reliable SLC program and read have a market need. It is desired to have an improved NAND program scheme, based on a novel NAND array structure with multi-level hierarchical bitlines, to replace the conventional iterative SLC program method with multiple-pulse stair-raised Vpgm including time-consuming program verification.